Field of the Invention
The present invention relates to a connecting technique for a semiconductor device in which a plurality of semiconductor chips, such as power semiconductor devices, are provided on a substrate.
Description of the Background Art
In such a semiconductor device, a metal heat spread is provided over a metal base plate with an insulating layer therebetween, and semiconductor chips such as IGBTs and diodes are bonded on the heat spread with solder. Methods for connecting such a plurality of semiconductor chips include wire bonding in which connections are made with wires like aluminum wires (see Japanese Patent Application Laid-Open No. 11-086546 (1999)) and direct lead bonding in which a lead frame is directly connected to the semiconductor chips (DLB; see Japanese Patent Application Laid-Open No. 2007-142138).
For wire bonding, the number of wires increases when an increased number of chips are provided on the substrate, and then the productivity is lowered.
For DLB, the resistance and inductance components are reduced as compared with wire bonding, and it has the advantage of high heat cycle property. However, when connections are made with a plurality of chips, the solder thicknesses in bonded portions vary and then the heat cycle property is lowered. Also, complicated bending processing is necessary in order to adapt to a plurality of chips. This increases the number of molding process steps with molds and increases manufacturing costs.
At present, semiconductor devices using materials capable of high-temperature operations, typically SiC, are under development, and structures stably connecting a plurality of chips at high temperatures are demanded.